1. Field of the Invention
The present invention relates generally to data communications, and, in particular, to a method and system for compensating for transmission line length variations in a serializer/deserializer (SERDES) transmission channel, such as a backplane.
2. Description of the Related Art
As data transmission rates continue to increase, parallel data transmission in backplane and other interconnect applications suffers from effects such as co-channel interference and electromagnetic interference (EMI). To correct for problems associated with high-speed parallel data transmission, parallel data may be serialized before transmission and then de-serialized upon reception. To achieve the transition between parallel and serial data transmission, serializer/deserializer (SERDES) devices are incorporated at both the transmitting and receiving ends of the serial data stream.
A SERDES device generally comprises at least one receiver and transmitter pair in the same core. The SERDES receiver is designed to receive serialized signals transmitted from a remote transmitter over a transmission channel, and convert the data into parallel format (deserializing) so the data may be further processed. The SERDES transmitter is designed to receive parallel data from the internal core, and serialize it for transmission to a remote receiver over the transmission channel.
FIG. 1 shows a block diagram of generic SERDES communication system 100. As shown in FIG. 1, SERDES communication system 100 comprises transmitting SERDES device 110, receiving SERDES device 120 and transmission channel 108. Parallel data stream u(n) is provided to transmitting SERDES device 110, where data stream u(n) is converted to a serial data stream by serializer 102. The serial data stream from serializer 102 is then modulated by modulator 104. The modulation may be a modulation technique such as non-return to zero (NRZ) modulation or higher level modulation techniques such as pulse amplitude modulation (PAM). The modulated signal from modulator 104 is then filtered by transmit finite impulse response filter (TXFIR) 106 before being provided to transmission channel 108. Transmission channel 108 might be a physical transmission medium such as a backplane. After passing through transmission channel 108, the transmitted signal is filtered and equalized by receive equalizer (RXEQ) 111, which might be, for example, a continuous-time filter. The output of RXEQ 111 is sampled using a sample clock recovered from the transmitted data by clock and data recovery circuit (CDR) 112. CDR 112 might typically be implemented as an adaptive feedback circuit to adjust the phase and frequency of the recovered clock to allow proper data recovery. Data recovery is performed by a data detector (not shown in FIG. 1). The data detector is often a slicer that is clocked by the recovered clock to quantize the sampled data to a binary 1 or 0 based upon a threshold amplitude. The detected data may then be provided for additional processing, such as decision feedback equalization (DFE) (not shown in FIG. 1). The detected serial data may then be converted to parallel data by serial to parallel converter 114, which provides parallel data stream u′(n).
In FIG. 1, transmission channel 108 and analog SERDES components (e.g. 102, 104, 106, 111, 112, 114) are shown as 1-port devices, meaning that there is one input port and one output port related by a single transfer function. However, at high data rates, transmission channel 108 and/or analog SERDES components may behave as 2-port transmission lines, where multiple inputs and outputs are related by multiple transfer functions.
As shown in FIG. 2, transmitting SERDES device 110, transmission channel 108 and receiving SERDES device 120 of FIG. 1 may be represented as a cascade of 2-port components. Transmitting SERDES device 110 comprises ideal transmitter 202 and transmitter load 204. Transmission medium 108 comprises transmitter package 206, transmission channel 208 and receiver package 211. Receiving SERDES device 220 comprises receiver load 212 and ideal receiver 214. As shown, ideal transmitter 202 and transmitter load 204 are located on the silicon chip of transmitting SERDES device 210. Transmitter package 206 represents the substrate that is used to house the silicon chip and to provide a physical interface between the silicon chip and a printed circuit board, wherein the printed circuit board also provides an interface to transmission channel 208. Similarly, receiver load 212 and ideal receiver 214 are located on the chip of receiving SERDES device 220, and receiver package 211 represents the substrate that is used to house the silicon chip and to provide a physical interface between the silicon chip and a printed circuit board, wherein the printed circuit board also provides an interface to transmission channel 208. The length of transmission channel 208 may vary in each SERDES communication system implementation, causing the overall length of transmission medium 108 to be variable.
A variation of the length of transmission medium 108 might cause a non-trivial change in the BER of a given receiver because, in general, a variation in the transmission channel length might be modeled equivalently by a delay. In a 1-port system, such a delay causes the output signal to be delayed by the same amount. However, in a 2-port system, such a delay changes the transfer function of the transmission channel.